Non-volatile memory devices find widespread application in electronic systems that do not receive continuous power, for example in applications where power is not always available, where power is frequently interrupted, and/or where low-power usage is desired. Example applications include mobile telecommunication systems, memory cards for storing music and/or image data, and system-on-a-chip applications that include a processing unit and a memory unit.
Cell transistors in non-volatile memory devices commonly employ a stacked gate structure that is formed over a channel region of a substrate between source/drain regions. The stacked gate structure includes a sequentially stacked gate insulating layer or “tunneling” layer, formed on the channel, floating gate electrode, inter-gate dielectric layer or “blocking” layer, and control gate electrode. The floating gate electrode and the control gate electrode are capacitively coupled to allow for programming of the floating gate during a programming stage of the transistor. At the same time, the floating gate electrode is isolated between the gate insulating layer and the inter-gate dielectric layer to prevent the migration of charge from the floating gate to the substrate or from the floating gate to the control gate during operation of the transistor following the programming stage.
Certain types of non-volatile memory devices include a SONOS structure formed of the sequential layers Silicon-Oxide-Nitride-Oxide-Silicon. An example of a SONOS structure is shown in FIG. 1. A channel region is formed on a silicon substrate 10 between source/drain regions 30a, 30b. A tunneling layer 12 formed of oxide, for example SiO2, is formed on the substrate 10. A nitride layer 14 is formed on the tunneling layer 12 and provides a charge-trapping layer that serves as a floating gate. A second oxide layer 16 is formed on the nitride layer 14, the second oxide layer 16 serving as a blocking layer. Together, the oxide tunneling layer 12, the nitride floating gate layer 14 and the oxide charge-trapping layer 16 form an oxide-nitride-oxide, or ONO, structure 20. A silicon layer 25 is provided on the second oxide layer 16 as a control gate electrode. SONOS-type non-volatile memory devices have relatively thin cells which are inexpensive to manufacture and can be readily incorporated into both a peripheral region and/or a logic region of an integrated circuit.
During a charging operation, a large positive voltage is applied to the control gate relative to the substrate. Electrons migrate from an inversion channel region or drain region through the channel region and penetrate into the nitride floating gate through the tunneling oxide layer. Electrons from the semiconductor substrate thereby become trapped in the nitride trapping layer. Since, during the programming operation, a higher bias voltage is applied to the drain relative to the source, a high concentration of electrons accumulates in the nitride trapping layer in the region proximal to the high-biased drain. Conversely, during a discharge operation, a negative voltage is applied to the control gate, and a positive voltage is applied to the substrate. During a discharge operation, the electrons previously stored in the floating gate are released back into the substrate through the gate insulating layer. Holes from the semiconductor substrate thereby become trapped in the trapping layer. Since, during the discharge operation, a higher bias voltage is applied to the drain relative to the source, a high concentration of holes accumulates in the nitride trapping layer in the region proximal to the high-biased drain. The amount of electrons or holes in the nitride floating gate trapping layer changes the threshold voltage of the transistor. In this manner, a charged transistor is interpreted as a first binary value, for example, a “1”, and a discharged transistor is interpreted as second binary value, for example, a “0”, during a read operation of the transistor.
Since the ONO structure exists across the entire channel region, the SONOS transistor of FIG. 1 above has a high initial threshold voltage, which leads to corresponding high power consumption in the device, and a high programming current. As a result, such a configuration does not apply well to system-on-a-chip products, which commonly require low power consumption, especially for portable applications that rely on battery power. In addition, electrons trapped in the nitride floating gate can migrate laterally along the nitride layer; as a result, an erase operation may not completely remove the electrons from the floating gate, which can adversely affect the threshold voltage of the transistor during a subsequent read operation.
To address these limitations, local-length nitride and thin-gate oxide transistors have been developed, as shown in FIG. 2. In this configuration, drain regions 68b are positioned on each side of a source region 68a in a semiconductor substrate 50. Two gate structures are formed simultaneously on adjacent channel regions on each side of the central source region 68a. A thin gate oxide layer 52 is provided on the channel region between the source 68a and drain 68b regions. A local-length nitride layer 54 is on the gate oxide layer 52 in a region that is proximal to the drain 68b. A blocking oxide layer 58 is on the local-length nitride layer 54. A control gate 65, for example formed of polysilicon, covers the resulting ONO structure 62.
In this configuration, the local-length nitride trapping layer 54 prevents lateral movement of electrons during a discharge operation, and therefore the reliability of the threshold voltage is improved. In addition, thin gate oxide layer 52 allows for a lower threshold voltage. However, the operating characteristics of the SONOS cell are highly dependent on the nitride length; for example, threshold voltage can vary considerably with varying nitride length. Since the conventional processes rely on photolithographic techniques to define the length of the nitride trapping layer, the processes are subject to misalignment. As shown in FIG. 2B slight misalignment of the photolithographic masks for forming the nitride trapping layer 52 can lead to adjacent devices having radically different nitride layer lengths L1, L2. This, in turn, can lead to significant variation in characteristics of the resulting transistors, including significant variation in threshold voltage.